The invention relates generally to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a semiconductor device through Spacer Patterning Technology (SPT) based on Multi Exposure Technology (MET).
In general, a process of producing semiconductor devices includes separate processes of fabrication, electrical die sorting, assembly, test, and so forth.
The fabrication process includes procedures for manufacturing a semi-manufactured product which is formed as electric circuits by repeatedly going through diffusion, photoresist patterning, etching, and deposition processes, which may be carried completely in the wafer state.
The electrical die sorting process begins after the fabrication process. The electrical die sorting process sorts out bad chips through a test of the electrical characteristics of each chip in the wafer state.
Meanwhile, as the degree of integration of semiconductor devices has increased, the size and pitch of patterns that form circuits have been reduced. According to Rayleigh's equation, the size of a fine pattern in a semiconductor device is in proportion to the wavelength of light used in the photo lithography process and is in inverse proportion to the size of the lens used in such a process. Thus, methods for reducing the wavelength of light used in the photo lithography or enlarging the size of lens have been used to reduce size and pitch of fine patterns.
In addition, as semiconductor devices have become highly-integrated, it would be necessary for manufacturing apparatus to operate beyond performance and capacity limits. In order to overcome technical limits of the manufacturing equipment, numerous methods have been attempted. For example, the amount of light, e.g. laser, injected into a semiconductor wafer through a reticle or a mask has been adjusted or controlled by designing the reticle or the mask to be finer in size. Also, researching of new photosensitive materials useful for pattern masks, development of scanners having a high numerical aperture lens, and development of deformed masks which contain a plurality of patterns in abnormal shapes have been attempted.
However, it is no longer possible to form desired width and pitch of fine patterns in a photo lithography process using the currently available light sources, e.g., KrF and ArF. For instance, currently developed photo lithography can form fine patterns having a size of at least about 60 nm on a semiconductor wafer, but there is much difficulty in making patterns having a size of less than 60 nm.
Thus, various studies have been conducted of processes to form finer photo resist patterns, made through the photo lithography, for using an etching mask during a process of etching an etch target layer in order to form finer patterns over the semiconductor wafer.
One such process is Double Patterning to form a pattern by using photo resist patterns made through carrying out photo lithography twice as an etching mask, and another is a Spacer Patterning Technology (SPT) to form a pattern by using a spacer. Generally, a spacer formed on sidewalls of various patterns in a semiconductor device has a thickness of from 20 nm to 30 nm. The spacer patterning technology using such spacers as an etching mask can form finer patterns than the double patterning using photo resist patterns as an etching mask, because it is possible that the spacers have smaller size than the photo resist patterns. A conventional spacer patterning technology explained in detail below.
FIGS. 1a to 1e are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device having a fine pattern through SPT.
Referring to FIG. 1a, a photoresist film is coated on an etching target layer 2. Then, a photomask is aligned with the etching target layer, and ultraviolet (UV) light is injected through windows in the photomask to form a photoresist pattern 4. This is generally called an exposure step. Through the exposure step, a photoresist exposed by a photomask becomes soluble and can be easily removed by the developer chemical used in a developing process Typically, the developing process includes a soft bake step, a wet etch developing step, and a hard bake step.
Referring to FIGS. 1b and 1c, after a spacer 6 is form on sidewalls of the photoresist pattern 4, and the photoresist pattern 4 is removed.
Referring to FIGS. 1d and 1e, the etching target layer 2 is etched by using the spacer 6 as an etching mask, and the spacer 6 is removed. Here, the critical dimension (CD) of a fine pattern 8 is determined by the thickness of the spacer 6. That is, the fine pattern 8 has the same CD to the thickness of the spacer 6.
However, in the conventional SPT described above, it is impossible for the thickness of the spacers formed on sidewalls of photoresist patterns to be different from each other. Thus, all spacers have the substantially same thickness, thereby being unable to form fine patterns having variable sizes.